The present invention relates to a semiconductor integrated circuit, and more particularly relates to an improved semiconductor integrated circuit including an interval voltage step down circuit.
In recent years, a device like a transistor included in a semiconductor integrated circuit has been continuously and drastically downsized, and therefore the breakdown voltage of the transistor has been decreasing. It is necessary to ensure required reliability for such a transistor and it is also required to operate the circuit with even lower power consumption. Thus, a semiconductor integrated circuit including an internal voltage step down circuit for stepping down an external power supply voltage inside the circuit and for driving the internal circuit thereof with the stepped-down voltage has gained a dominant position in the pertinent art lately.
Also, in general, in order to distinguish good semiconductor integrated circuit products from defective ones, an operation margin certification test is carried out. In such a test, it is determined whether or not the semiconductor integrated circuit operates in such a manner as to satisfy the required specifications by applying, to the semiconductor integrated circuit, a voltage several percent higher than the upper limit or several percent lower than the lower limit of the operability assuring voltage range of the semiconductor integrated circuit by the use of a memory tester or a logic tester. Also, in order to effectively screen the early failure of a semiconductor integrated circuit, an accelerated test, i.e., a so-called "burn-in test", is carried out. In the test, a voltage exceeding the operability assuring voltage range of the semiconductor integrated circuit is applied thereto for a predetermined period of time at a high temperature.
Hereinafter, the characteristics of conventional semiconductor integrated circuits will be described.
The characteristics of an internal power supply voltage VINT with respect to an external power supply voltage VEXT applied to a semiconductor integrated circuit including an internal voltage step down circuit are classified into the three types illustrated in FIGS. 20A, 20B and 20C, respectively. In any of the three types of characteristics, while the external power supply voltage VEXT is in the range from "0" to a predetermined value V1, the internal power supply voltage VINT rises in proportion to the external power supply voltage VEXT. On the other hand, while the external power supply voltage VEXT is in the range from the predetermined value V1 to another predetermined value V2, the internal power supply voltage VINT is at a constant value VA. Thus, if the operability assuring voltage range of the external power supply voltage applied to a semiconductor integrated circuit is equal to or larger than the predetermined value V1 and smaller than the predetermined value V2, the internal circuit thereof is driven with the constant voltage VA. As a result, the semiconductor integrated circuit can operate stably without depending on the external power supply voltage. However, on and after the external power supply voltage VEXT reaches the predetermined value V2, the internal power supply voltage VINT, which has been the constant voltage VA so far, will go on rising in proportion to the external power supply voltage VEXT. Such voltage characteristics are typically exhibited during an accelerated test and determined for the purpose of increasing the voltage to be applied to the internal circuit during the accelerated test by increasing the internal power supply voltage, which has been the constant voltage VA till then. In the case of FIG. 20A, as soon as the external power supply voltage VEXT reaches the predetermined value V2, the internal power supply voltage VINT rises from the constant voltage VA to a voltage VB. Then, the internal power supply voltage VINT goes on rising at the same rise rate as that of the external power supply voltage VEXT. In the case of FIG. 20B, as soon as the external power supply voltage VEXT reaches the predetermined value V2, the internal power supply voltage VINT rises from the constant voltage VA to a voltage VC. Then, the internal power supply voltage VINT goes on rising from the voltage VC in proportion to the external power supply voltage VEXT. In the case of FIG. 20C, when the external power supply voltage VEXT reaches the predetermined value V2, the internal power supply voltage VINT starts rising from the constant voltage VA in proportion to the external power supply voltage VEXT.
FIGS. 19A, 19B and 19C are block diagrams illustrating exemplary configurations of the semiconductor integrated circuits corresponding to the three types of characteristics illustrated in FIGS. 20A, 20B and 20C, respectively.
In FIGS. 19A, 19B and 19C, the reference numeral 1 denotes a reference voltage generator; 2 denotes an accelerated test detector; 3 denotes a P-type MOS transistor; 4 denotes a reference voltage selector; 5 denotes an internal power supply circuit; 6 denotes an internal circuit; VREF1, VREF2, VREF3 denote reference voltages; VBI2 denotes an output signal of the accelerated test detector 2; VINT denotes an internal power supply voltage; and VEXT denotes an external power supply voltage. The respective operations of the semiconductor integrated circuits having such configurations will be described.
First, the operation of the semiconductor integrated circuit illustrated in FIG. 19A will be described. The reference voltage generated by the reference voltage generator 1 is constant at VA on and after the external power supply voltage VEXT reaches the predetermined value V1 as shown in FIG. 21A, and is output as the reference voltage VREF1. The accelerated test detector 2 determines whether or not an internal power supply voltage for an accelerated test should be generated. If the external power supply voltage VEXT is smaller than the predetermined value V2, the accelerated test detector 2 outputs a high-level signal as the output signal VBI2. On the other hand, on and after the external power supply voltage VEXT reaches the predetermined value V2, the accelerated test detector 2 outputs a low-level signal. Thus, the P-type MOS transistor 3, receiving the output signal VBI2 of the accelerated test detector 2 at the gate terminal thereof, is in the OFF state while the external power supply voltage VEXT is in the range from "0" to V2. On the other hand, on and after the external power supply voltage VEXT reaches V2, the P-type MOS transistor 3 is in the ON state. As a result, the reference voltage VREF1 has the characteristics shown in FIG. 21A while the external power supply voltage VEXT is in the range from "0" to V2, but comes to have the same characteristics as those of the external power supply voltage VEXT on and after the external power supply voltage VEXT reaches V2, because the P-type MOS transistor 3 is in the ON state. And based on the reference voltage VREF1, the internal power supply circuit 5 supplies the internal power supply voltage VINT for driving the internal circuit 6.
In this case, the internal power supply circuit 5 is generally constituted by a differential amplifier 7 and a P-type MOS transistor QP3 as shown in FIG. 22. In FIG. 22, the differential amplifier 7 includes: a pair of P-type MOS transistors QP1, QP2 constituting a current mirror; a pair of N-type MOS transistors QN1, QN2 serially connected to the P-type MOS transistors QP1, QP2, respectively; and an N-type MOS transistor QN3 for controlling the current flowing through the differential amplifier 7. The reference voltage VREF1 is applied to one input of the differential amplifier 7, i.e., the gate terminal of the N-type MOS transistor QN1. The internal power supply voltage VINT, which is the drain voltage of the P-type MOS transistor QP3, is applied to the other input of the differential amplifier 7, i.e., the gate terminal of the N-type MOS transistor QN2. The output of the differential amplifier 7, i.e., the drain voltage of the P-type MOS transistor QP1, is applied to the gate terminal of the P-type MOS transistor QP3.
Hereinafter, the operation of the internal power supply circuit 5 having the above-described configuration will be described.
As described above, the differential amplifier 7 receives the reference voltage VREF1 and the internal power supply voltage VINT as inputs. If the internal power supply voltage VINT is lower than the reference voltage VREF1, then the differential amplifier 7 outputs a low-level signal, turns ON the P-type MOS transistor QP3 on the next stage and then supplies the external power supply voltage VEXT as the internal power supply voltage VINT. On the other hand, if the internal power supply voltage VINT is higher than the reference voltage VREF1, then the differential amplifier 7 outputs a high-level signal and turns OFF the P-type MOS transistor QP3 on the next stage. By controlling the ON/OFF states of the P-type MOS transistor QP3 in this manner, the internal power supply voltage VINT, which is the drain voltage thereof, becomes equal to the reference voltage VREF1. The characteristics shown in FIG. 20A are exhibited by such a configuration.
Next, the operation of the semiconductor integrated circuit illustrated in FIG. 19B will be described. The reference voltage generator 1 generates two types of reference voltages VREF1 and VREF3. Of these two types of reference voltages generated, VREF1 has the characteristics shown in FIG. 21A in the same way as in the semiconductor integrated circuit shown in FIG. 19A. The other reference voltage VREF3 becomes equal to the reference voltage VC when the external power supply voltage VEXT is at the predetermined value V2, and then rises from VC in proportion to the external power supply voltage as shown in FIG. 21B. The accelerated test detector 2 performs the same operation as that performed by the counterpart in FIG. 19A and generates an output signal VBI2. The reference voltage selector 4 receives the two types of reference voltages VREF1 and VREF3 as inputs and selectively outputs one of them in response to the output signal VBI2 of the accelerated test detector 2. Assume the reference voltage selector 4 selectively outputs the reference voltage VREF1 when the output signal VBI2 is at a high level, and selectively outputs the reference voltage VREF3 when the output signal VBI2 is at a low level. In such a case, while the external power supply voltage VEXT is in the range from "0" to the predetermined value V2, the output of the reference voltage selector 4 exhibits the characteristics shown in FIG. 21A. On the other hand, on and after the external power supply voltage VEXT reaches the predetermined value V2, the output of the reference voltage selector 4 exhibits the characteristics shown in FIG. 21B. And, based on the reference voltage output from the reference voltage selector 4, the internal power supply circuit 5 generates the internal power supply voltage VINT for driving the internal circuit 6. The characteristics shown in FIG. 20B are exhibited by such a configuration.
Next, the operation of the semiconductor integrated circuit shown in FIG. 19C will be described. The reference voltage generator 1 generates two types of reference voltages VREF1 and VREF2. Of these two types of reference voltages, VREF1 has the characteristics shown in FIG. 21A in the same way as in the semiconductor integrated circuits shown in FIGS. 19A and 19B. That is to say, on and after the external power supply voltage VEXT reaches the predetermined value V1, the reference voltage VREF1 is constant at VA. The other reference voltage VREF2 becomes equal to the reference voltage VA when the external power supply voltage VEXT is at the predetermined value V2 and then rises from VA in proportion to the external power supply voltage VEXT as shown in FIG. 21C. And, based on either one of the two types of reference voltages generated VREF1 and VREF2 that is the higher one with respect to the same value of the external power supply voltage VEXT, the internal power supply circuit 5, receiving the higher reference voltage, outputs the internal power supply voltage VINT for driving the internal circuit 6. Specifically, while the external power supply voltage VEXT is smaller than the predetermined value V2, the internal power supply voltage VINT to be generated has the characteristics shown in FIG. 21A. On the other hand, on and after the external power supply voltage VEXT reaches the predetermined value V2, the internal power supply voltage VINT to be generated has the characteristics shown in FIG. 21C. The characteristics shown in FIG. 20C are exhibited by such a configuration.
The conventional semiconductor integrated circuits, however, have the following problems.
First, in the case of FIG. 20A, as soon as the external power supply voltage VEXT reaches the predetermined value V2, the internal power supply voltage VINT abruptly rises from the constant voltage VA to the voltage VB. That is to say, since such a semiconductor integrated circuit has discontinuous voltage characteristics, the characteristics of the internal circuit to be driven with the internal power supply voltage VINT in the range from VA to VB cannot be certified. Thus, in the operation margin certification test, the operation of the internal circuit cannot be assured unless the internal power supply voltage VINT is equal to or smaller than VA or equal to or larger than VB.
Next, in the case of FIG. 20B, as soon as the external power supply voltage VEXT reaches the predetermined value V2, the internal power supply voltage VINT abruptly rises from VA to VC. That is to say, since such a semiconductor integrated circuit also has discontinuous voltage characteristics, the same problems as those of FIG. 20A are caused.
Finally, in the case of FIG. 20C, even after the external power supply voltage VEXT has reached the predetermined value V2, the internal power supply voltage VINT has continuously varying voltage characteristics, unlike the discontinuous voltage characteristics shown in FIGS. 20A and 20B. Thus, the problems involved with the cases shown in FIGS. 20A and 20B can be avoided. However, the rise rate of the internal power supply voltage VINT after the external power supply voltage VEXT has reached the predetermined value V2 is lower than those of FIGS. 20A and 20B. Thus, the voltage to be applied to the internal circuit cannot be increased at a sufficiently high rate during the accelerated test.